Computers and data processing systems of the future will in general need to be designed for operating speeds substantially higher than those of present day equipment. The operating speed of single processors has reached a limit that is not likely to be sufficiently extended with foreseeable technology to meet these future requirements. A common approach has been to use multi-processor systems in which theoretically the operating speed of the system is the sum of the speeds of the individual multi-processors. One form of such a multi-processor system is illustrated in FIG. 1 in which there are multiple processors 10, each having an associated fast cache memory 12 and a larger but slower local memory 14. One or more of the processors may be dedicated to particular functions for the entire system, such as input/output or supporting a bulk memory. The processors 10 are operating fairly independently of each other and communicate with each other by sending transmissions over channels 16 through a common switch 18.
The function of the switch 18 is, under the control of a command sent from a requesting processor, to connect the channel 16 from the requesting processor 10 to the channel 16 to another designated process 10. Thereby the two processors 10 are in momentary communication. Once the communication, perhaps involving a response, has been completed, the switch 18 disconnects the channels 16 connecting the two processors 10.
The communication between the processors 10 can have widely varying characteristics. A processor 10 may want to send a large number of short messages to one or more other processors 10. Each message requires a connection to be made and broken in the switch 18. On the other hand, fairly large blocks of data may need to be transferred between processors 10. Once choice for data transfer is to organize the data in pages, each page containing 4 kilobytes of data. It is desirable that the entire transfer of the page of 4 kilobytes occurs in less than 10 microseconds. It must be remembered that the data path in a large data processing complex can easily extend for 100 meters which translates to a propagation time of 0.5 microsecond for a 5 nanosecond per meter channel.
It is seen that the switch 18 is the central element of the illustrated multi-processor system. While the processors 10 can be multiplied for increased speed and capacity, all information flow is through the switch 18. Thus the switch 18 is likely to be the limiting factor for a high speed, large-scale data processing complex.
The processors 10 of such a system would each be operating in the range of 50 to 100 MIPs. The channels between the processors 10 are likely to be optical fiber paths. At the present time, data rates of 100 megabits per second appear feasible and it is likely that fiber optic data rates will be extended into the multi-gigabit range. These speeds will put an extreme demand upon the switch 18 of a multi-processor system and such switch speeds appear unavailable with conventionally designed switches.
The switch 18 should also have a flexible design. Short messages and large blocks of data put different demands upon the switch 22. Although the short messages require only a lower bandwidth, a high frequency of messages will require that the set-up time in the switch 18 be minimized. Furthermore, a typical data processing complex is not designed as an entity. Instead, additional processors 10 are added as greater demands are put upon the system. Furthermore, when newer and faster processors and communication channels become available, they are likely to be added onto an existing system rather than to replace the existing and slower components. As a result, the switch 18 should have the capability of providing both incremental bandwidth as well as variable bandwidth depending upon interconnection being made. No such variable bandwidth switch is known to be currently available.
One of the advantages of the multiprocessor system of FIG. 1 is the system reliability afforded by the multiplicity of the processors 10. If one processor 10 or associated channel 16 fails, the remaining processors 10 can continuing operating. Although the system performance is degraded by the loss of the failed component, there are a sufficient number of remaining operable components so that the system performance remains satisfactory. Alternatively, spare processors 10 can be included in the system to replace any failed component. High reliability is particularly required in large data processing complexes such as credit card or banking operations which support a large number of terminals in real time. The switch 18 of the illustrated multi-processor system however, presents a single point failure. Accordingly, a mean time between failure of 100 years for the switch 18 is not an unreasonable requirement.
Such reliability is not considered available in the current cross-point switches.